Single Electron Transistors

K. Matsumoto


Recently, single electron transistors (SETs) have come to be considered candidates as elements for future low power, high density integrated circuits because of their potential for ultra-low power operation involving only a few electrons. In order to be useful in practical applications, however, SETs must be operable at room temperature. Capacitance and thermal fluctuation limitations require that the island size of the SET be no larger than ~10 nm, a feature size out of the range of present conventional microfabrication processes.

Room temperature operation of single electron memory has been realized by the use of self-organized, small-size structures on thin poly-silicon films.1 However, it is difficult to control the size and structure of the SET island with the spontaneous size formation fabrication method.

Earlier, we demonstrated an artificial pattern formation method based on the scanning tunneling microscope (STM) which avoids the control problems in self- organized structures.2 Using this technique, we have succeeded in fabricating an SET. The SET operates at room temperature, showing a clear Coulomb staircase with a ~150 mV period at 300 K.

SET Fabrication

Figure 1.) Fabrication of the Ti/TiOx SET by the STM nano-oxidation process.

A description of the STM nano-oxidation process3 is shown in figure 1. A 3 nm thin titanium (Ti) metal film is deposited on a 100 nm thermally oxidized SiO2/n-Si substrate. The Ti surface was oxidized by anodization through the water adhered to the surface of the Ti from the atmosphere, using the STM tip as a cathode, forming nanometer size Ti oxide (TiOx) lines. The barrier height of the TiOx/Ti junction has been found to be 285 meV for the electron from the temperature dependence of the current. 3 The relative permittivity of the TiOx has been determined as er = 24 from the electric field dependence of the TiOx barrier height.4

SET Schematic

Figure 2. Schematic of a single electron transistor

Figure 2 shows a schematic illustration of the SET made by the STM nano- oxidation process. At both ends of the 3 nm thick Ti layer we formed the source and drain ohmic contacts, and on the back side of the n-Si substrate, we formed the gate ohmic contact. At the center region of the Ti layer, we formed the island region, surrounded by two parallel, narrow TiOx lines, that serve as tunneling junctions for the SET, and two large TiOx barrier regions. Figure 3 is an atomic force microscopy (AFM) image of the island region of a fabricated SET.

AFM image

Figure 3. AFM image of a single electron transistor made by the STM nano-oxidation process

Typical sizes of the TiOx lines are 15-25 nm widths and 30-50 nm lengths. Typical island sizes are 30-50 nm by 35-50 nm. The most important feature of this structure is the small tunnel junction. The junction area corresponds to the cross section of the TiOx line, and is as small as 2-3 nm (the thickness of the Ti layer) by 30-50 nm (the length of the TiOx line). The deposited Ti layer is as thin as 3 nm, and the surface of the Ti layer is naturally oxidized to a depth of ~1 nm. Thus, the intrinsic Ti layer thickness is considered to be less than 3 nm. Owing to this small tunneling junction area, the tunnel capacitance becomes as small as 10-19 F, which allows the SET to be operated at room temperature.

SET I-V Plot

Figure 4. Drain current v. drain voltage characteristics of the SET at 300 K

The drain current-voltage characteristics of the SET were measured at room temperature and are shown in figure 4. The gate bias was set to 2 V. In the figure, the solid lines shows the current of the SET, and the dashed line shows the conductance of the SET. Between the drain bias of 0 V and -0.75 V, four clear Coulomb staircases with a ~150 mV period are observed. The conductance oscillates with the increase of the drain bias with almost the same 150 mV period. The lower peaks of the conductance oscillation correspond to the flat regions of the current of the Coulomb staircase.

The Coulomb staircase shown in figure 4 may be attributed to the asymmetrical structure of the two tunneling junctions. One TiOx tunneling junction has a width of 18 nm, while the other junction is 27 nm wide. Due to this difference in junction widths, each tunneling junction has different values of conductance and capacitance, which produces the Coulomb staircase.

The height of the Coulomb steps becomes larger with larger applied drain bias. This may be attributed to the increase of the tunneling probability of the electron through the TiOx tunneling barrier. The Fowler-Nordheim tunneling current increases as the applied drain bias lowers the height of the TiOx tunneling barrier.

The drain current v. gate bias characteristics with 150 mV drain bias at room temperature exhibit clear current oscillations with a period of ~460 mV, implying a periodic Coulomb oscillation of the current. The tunneling capacitance (Ct) and gate capacitance (Cg) could be roughly estimated from the period of the Coulomb staircase and oscillation. Their values were found to be Ct = ~3.6 x 10-19 F and Cg = ~3.5 x 10-19 F. These estimated values of the capacitances coincide well with the calculated capacitances from the SET's structural parameters. These results confirm the existence of Coulomb blockade phenomena at room temperature, and are due to the small dimensions of the SET island formed by the STM nano-oxidation process.

In conclusion, we have succeeded in fabricating a room temperature- operable single electron transistor using the STM nano-oxidation process. The SET shows a Coulomb staircase with periods of 150 mV at a temperature of 300 K. The Coulomb gap and staircase observed at high temperatures are attributed to the small tunneling junction area made by the STM nano- oxidation process. The fabrication process is quite easy and could be applicable to many kinds of devices.


References

1. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai and K. Seki, Technical Digest of the 1993 International Electron Device Meeting, 541 (1993).

2. K. Matsumoto, S. Takahashi, M. Ishii, M. Hoshi, A. Kurokawa, S. Ichimura, and A. Ando, Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, Japan, 46 (1994).

3. K. Matsumoto, S. Takahashi, M. Ishii, M. Hoshi, A. Kurokawa, S. Ichimura, and A. Ando, Japanese Journal of Applied Physics 34, 2B, 1387 (1995).

4. K. Matsumoto, M. Ishii, J. Shirakashi, Y. Oka, A. Kurokawa, and S. Ichimura, Applied Physics Letters (to be published).


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